1. Field of the Invention
The present invention is generally in the field of semiconductor fabrication and more particularly in the field of semiconductor chip packaging.
2. Background Art
A leadframe is used, for example, in the fabrication of plastic molded enclosures, also referred to as a xe2x80x9cmolded packagexe2x80x9d or a xe2x80x9cleadframe packagexe2x80x9d in the present application. The leadframe can be fabricated from a metal, for example, copper, and typically comprises a paddle which is secured to the body of the leadframe and typically situated at the center of the leadframe. The leadframe also comprises a number of leads which are secured to the frame. In an xe2x80x9cexposedxe2x80x9d paddle leadframe based molded package, the bottom of the paddle of the leadframe is left exposed in order to attach the bottom of the paddle to a printed circuit board.
Flip chip technology is a surface mount technology in which the semiconductor die is xe2x80x9cflippedxe2x80x9d over such that the active surface of the die faces downward to the interconnect substrate. Electrical contact between the active surface of the die and the interconnect substrate is achieved by utilizing an area array of small solder xe2x80x9cbumpsxe2x80x9d that are planted on pads on the active surface of the die. After the die is placed faced down on the interconnect substrate, the temperature is increased and the solder in the flip chip solder bumps reflows, bonding the die directly to the interconnect on the substrate. As such, the die makes electrical and mechanical connection directly to the interconnect substrate without the use of bond wires. Flip chip technology provides a configuration that eliminates wire bonding and allows shorter interconnections between circuits and components, which results in thermal, electrical, and mechanical advantages. The solder reflow bonding process in flip chip fabrications is not always reliable, however, and the solder may flow outward from the pads and cause defects that can affect yield or performance.
Although flip chip technology is quite advantageous for applications with high heat dissipation and large pin counts, the process is complicated and expensive for low pin count specialty applications where high heat dissipation is desired. Such specialty chips may be in the form of small dies that may have only 10 pin-outs, versus over 100 pin-outs for larger or more complex dies, for example. Gallium arsenide (GaAs) power amplifier chips used in radio frequency (RF) applications are an example of low pin count devices that require a relatively high level of heat dissipation. Reliable performance, good heat dissipation, and low cost are critical factors in the design of RF devices. Two primary techniques currently exist for the fabrication of low pin count devices, although neither is free of considerable drawbacks.
One technique utilizes flip chip technology on a laminate substrate and the other utilizes a paddle with wire bonding. The first technique, i.e. flip chip on laminate, is shown in FIG. 1A. Flip chip on laminate employs a grid of solder bump pads on a laminate printed circuit board (PCB). Die 112 represents a die that has been flipped over and bonded onto laminate PCB 114 by solder bumps 110. FIG. 1B is a bottom view of die 112 as shown in FIG. 1A, illustrating the area array of solder bumps 110 on the active surface of the die. Since multiple layers of interconnect metal are required in PCB 114 for the numerous pin-out connections, vias 118 and 120 are exemplary vias used to reach respective layers of interconnect metal. Since laminate materials, e.g. bismaleimide triazine (BT) or BT impregnated glass weaves, used in PCB 114 are not good thermal conductors, the flip chip on laminate PCB has poor heat dissipation characteristics. The use of a laminate PCB is also expensive for low pin count applications.
The second technique utilizes a paddle instead of a laminate PCB, but uses wire bonding. Although the paddle exhibits good thermal conduction, the use of wire bonds introduces high electrical inductance and electrical resistance. Additionally, the wire bonding process does not produce optimal electrical contact and mechanical stability.
Thus there is need in the art for a low cost flip-chip package, with low thermal and electrical resistance and improved mechanical stability.
The present invention is directed to a structure for semiconductor die packaging. The invention overcomes the need in the art for a low cost flip-chip package, with low thermal and electrical resistance and improved mechanical stability.
According to one embodiment of the present invention, a leadframe includes at least one peripheral lead secured to a paddle. The leadframe can be fabricated from an electrically and thermally conductive metal such as copper. A paddle solder bump pad and a peripheral solder bump pad are respectively situated on the at least one peripheral lead and the paddle. A first recess is adjacent to the paddle solder bump pad and a second recess is adjacent to the peripheral solder bump pad. In one embodiment, the first and second recesses can be, for example, in the shape of rings encircling respectively the paddle solder bump pad and the peripheral solder bump pad. The first and second recesses can be fabricated, for example, by a chemical etch process.
In one embodiment, a semiconductor die having at least first and second solder bumps is situated on the leadframe such that the first solder bump is soldered to the paddle solder bump pad while the second solder bump is soldered to the peripheral solder bump pad. The first and second solder bumps can comprise, for example, tin or a tin/lead alloy.
The first and second recesses adjacent to respectively the paddle solder bump pad and the peripheral solder bump pad prevent solder from flowing out of the solder bump pad areas during solder reflow process. In this manner, the potential shorting of adjacent solder bump pads is prevented. Thus, the semiconductor die is electrically, mechanically, and thermally secured to the leadframe while resulting in a low cost flip-chip package, with low thermal and electrical resistance and improved mechanical stability.